The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a highly integrated semiconductor device with improved operation and reliability by forming an air tunnel in the lower part of the transistor channel.
Generally, to form a PN junction, n-type or p-type impurities are injected in a p-type or n-type diffusion region of a semiconductor substrate, and the impurities are activated by a thermal treatment.
Accordingly, in a semiconductor device with a reduced channel width, the junction should be formed with a shallow depth to prevent a short channel effect resulting from side-diffusion from the diffusion region.
A conventional method for fabricating a MOS field effect transistor is as follows.
First of all, a device isolation layer is formed on a semiconductor substrate, and a gate insulation layer and a polysilicon layer are formed on the semiconductor substrate.
Then, a gate electrode is formed by etching the polysilicon layer and the gate insulation layer with a gate electrode mask, which is used as an etching mask.
Subsequently, a lightly doped drain (LDD) region is formed by ion-injecting low-concentration impurities in the semiconductor substrate at both sides of the gate electrode.
Thereafter, an insulation layer is formed on the semiconductor substrate, and spacers are formed on sides of the gate electrode by etching the isolation layer.
A MOS field effect transistor is formed by forming a source/drain region after highly concentrated impurities are ion-injected into the semiconductor substrate at both sides of the insulation layer spacer.
In the conventional method for fabricating a semiconductor device, the more integrated the device becomes, the shorter the channel grows. Punch-through occurs as the result of a drop of internal pressure between the sources and the drains. As a result, the drain current is not saturated even in the saturation region and increases along with an increase of the drain voltage. In addition, there is a problem that it is difficult to expect the device to work properly and serve the role of a control device, because the sub-threshold voltage decreases and thus electric current increases in the non-operation region.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device, which improves the operation properties and reliability by forming an air tunnel in the lower part of the transistor channel and improving the short channel effect and the ESD (electrostatic discharge) effect.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming a first semiconductor layer and a second semiconductor layer in order on a semiconductor substrate, wherein the first and the second semiconductor have different etch rates; forming a contact hole by selectively etching the second semiconductor layer, wherein a portion of the first semiconductor layer is exposed; forming an air tunnel by wet-etching the first semiconductor layer exposed through the contact hole; forming a third semiconductor layer on the second semiconductor layer and in the contact hole, wherein a channel region consisting of the second and the third semiconductor layers overlapped with the air tunnel is formed; forming a gate insulation layer and a gate electrode on the third semiconductor layer; and forming a source/drain region in the first to third semiconductor layers.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming a first semiconductor layer and a second semiconductor layer in order on a semiconductor substrate, wherein the first and the second semiconductor have different etch rates; forming a contact hole by selectively etching the second semiconductor layer, wherein a portion of the first semiconductor layer is exposed; forming an air tunnel by wet-etching the first semiconductor layer exposed through the contact hole; forming a third semiconductor layer on the second semiconductor layer and in the contact hole, wherein a channel region consisting of the second and the third semiconductor layers overlapped with the air tunnel is formed; forming a gate insulation layer and a gate electrode on the third semiconductor layer; forming a lightly doped drain region in the first to the third semiconductor layers at both sides of the gate insulation layer; forming spacers at sides of the gate electrode and the gate insulation layer; and forming a source/drain region in the first to the third semiconductor layers and in the semiconductor substrate at both sides of the spacers.